IPC-4761 does not treat via-in-pad as a casual layout trick. It classifies filled and capped vias as a distinct protection method, and that distinction matters because a via drilled straight through a solderable pad can ruin assembly yield if the structure is specified badly. In one common failure pattern, the bare board looks fine under AOI, but reflow leaves starved joints because solder has wicked into the hole.
That is the real split in via-in-pad decisions. Used correctly, via-in-pad solves dense BGA escape routing, lowers loop inductance in power layouts, and moves heat out of exposed pads. Used casually, it adds cost, longer lead time, and an assembly problem that did not need to exist.
This guide explains when via-in-pad is justified, when dog-bone fanout is the better answer, what VIPPO actually means on a fabrication drawing, and how to choose pad, via, fill, and stencil strategy without creating solder-wicking defects.
Defines via protection structures including Type VII filled and capped vias.
Infineon cites this as a typical thermal-via hole diameter range for exposed pads.
A practical starting pitch for thermal-via arrays in leadless package pads.
The IPC-recommended via protection style when specifying via-in-pad.
What Via-in-Pad Actually Means
Via-in-pad means the via barrel sits inside the solderable copper pad instead of next to it. In BGA escape routing, that lets you drop straight down from the ball pad into an inner layer. In QFN and power packages, it lets the exposed pad connect directly to inner copper for heat spreading, grounding, or current sharing.
The important engineering detail is that not all via-in-pad structures are equal. An open via drilled through a solderable pad is usually a defect generator. A filled, planarized, and copper-capped via is a manufacturable interconnect strategy. Those are completely different fabrication notes, with completely different yield outcomes.
Terminology that matters
Designers often say “via-in-pad” when they really mean VIPPO or filled and capped. On a fabrication drawing, that difference is not cosmetic. IPC-4761 identifies Type VII as the filled-and-capped structure recommended for via-in-pad applications.
"The expensive part of via-in-pad is not the drill. It is the moment a designer uses a premium process where a clean dog-bone breakout would have shipped faster, cheaper, and with less process risk."
Hommer Zhao
Founder & Technical Expert, PCB Insider
When Via-in-Pad Is the Right Choice
Via-in-pad earns its keep in four situations: fine-pitch BGA escape, exposed thermal pads, high-current power loops, and RF or very high-speed grounding structures where every millimeter of loop length matters. Intel explicitly documents via-in-pad as one breakout option for high-speed FPGA fanout, and Analog Devices shows vias placed directly on FET pads to reduce parasitic inductance and move heat into internal copper.
Fine-pitch BGA escape routing
When the package pitch gets tight enough that a standard dog-bone fanout consumes too much escape room, dropping directly from the pad can be the only practical route.
Exposed thermal pads on QFN, SON, and power devices
Leadless packages often need dense thermal vias under the center pad so heat can move into buried copper or the backside of the board.
Low-inductance current loops
Power conversion layouts use pad-level vias to shorten current return paths, reduce loop ESL, and improve switching behavior.
RF grounding and dense HDI interconnects
If signal integrity depends on an immediate layer transition or tight ground stitching, via-in-pad can outperform offset vias.
When Via-in-Pad Only Adds Cost
The simplest rule is this: if you can break out the part with a standard via next to the pad, do that first. Community discussions from practicing PCB designers repeat the same lesson: via-in-pad is powerful, but it becomes bad economics when used on roomy layouts where standard fanout is available.
The overkill trap
If your board has enough area to move the via outside the pad, you usually gain cheaper fabrication, easier rework, and less stencil tuning. Via-in-pad should solve a routing, thermal, or electrical constraint. It should not be the default aesthetic choice.
Dog-Bone vs. Via-in-Pad vs. VIPPO
The most useful comparison is not “via-in-pad good or bad.” It is which interconnect structure matches the package, assembler, and cost target. That is where most weak articles stop short.
| Approach | Best Use Case | Main Risk | Cost / Lead Time |
|---|---|---|---|
| Dog-bone fanout | 0.8 mm and many 0.65 mm BGA layouts, general SMT breakout | Consumes routing area around the pad | Lowest cost and fastest fab path |
| Open via in pad | Almost never acceptable for solderable SMT pads | Solder wicking, voids, starved joints, bottom-side solder bumps | Cheap bare board, expensive assembly failure |
| Filled via in pad | Thermal pads or controlled via protection cases | Planarity and fill quality still matter | Higher cost than standard vias |
| VIPPO / IPC Type VII | Fine-pitch BGA, premium thermal pads, high-speed or power layouts | Quote delta and tighter fabrication process window | Highest cost, but lowest assembly risk when truly needed |
The practical implication is simple. Open vias in pads are not a cheaper version of VIPPO. They are a different structure with a different failure mode. If the pad must remain solderable, call out a filled and planarized solution instead of hoping the assembler can compensate with paste volume.
"A via-in-pad note is incomplete unless it tells the fabricator what protection structure you want and tells the assembler what paste strategy you expect. Fabrication and assembly have to read the same intent."
Hommer Zhao
Founder & Technical Expert, PCB Insider
A Practical Decision Framework
Use this framework as a starting point. These thresholds are design heuristics, not IPC limits, and they should always be checked against your fabricator’s trace, space, drill, and fill capability.
If the package is 0.8 mm pitch or larger, start with standard dog-bone fanout before considering via-in-pad.
If the package is around 0.65 mm pitch, test whether your standard trace/space rules can still escape cleanly. Many boards can avoid via-in-pad here.
If the package is 0.5 mm pitch or below, evaluate HDI and via-in-pad early instead of forcing an unstable breakout late in layout.
If the via sits in a solderable pad, specify filled and capped protection. Do not leave the pad as an open plated hole.
If the goal is only thermal transfer under a center pad, start with a regular via array and segmented stencil pattern before jumping to full VIPPO on every hole.
If the product is low-volume prototype hardware and rework matters, ask whether a larger package or offset-via breakout will save more time overall.
Design Rules That Prevent Assembly Problems
Infineon’s board-assembly guidance for leadless packages is useful here because it focuses on what happens in real reflow, not just in CAD. It notes that solder penetration into thermal vias can reduce stand-off, increase voiding, and leave excess solder on the opposite side of the board. That is exactly why the stencil design, fill method, and via placement must be reviewed together.
Call out the via protection type
Use fabrication notes that name filled and capped vias instead of vague phrases like 'plug if needed.'
Coordinate stencil with the pad design
Large exposed pads need segmented paste windows so the center pad does not flood and trap large voids.
Match the structure to the use case
A thermal pad under a QFN does not always need the same via strategy as a 0.4 mm BGA breakout.
Review rework and inspection early
Dense via-in-pad layouts can be harder to rework, especially when the package leaves little visual solder evidence.
Thermal Pad Via Arrays: The Common Special Case
Many engineers first encounter via-in-pad under a QFN or power package center pad, not under a BGA ball. In that case, the design problem is different. You are not primarily chasing breakout density; you are balancing heat transfer, solder volume, and assembly yield.
Infineon gives a practical starting range of 0.2 mm to 0.5 mm via hole diameter and 1.0 mm to 1.2 mm pitch for thermal-via arrays. That is useful because it shows the right mindset: start with a reasonable thermal pattern, then optimize based on analysis and assembly results instead of blindly adding more holes. More vias do not reduce thermal resistance in a linear way, but they can increase solder-control problems quickly.
If your thermal pad can tolerate vias offset slightly from the highest-paste regions, you may be able to keep the thermal benefit without paying for premium filled-and-capped processing on every opening. That is often the best compromise on industrial and power boards.
"The correct question is not ‘can my fab make via-in-pad?’ It is ‘can my fab make this via-in-pad structure at the yield, flatness, and turnaround my assembly plan needs?’"
Hommer Zhao
Founder & Technical Expert, PCB Insider
Specification Checklist Before You Release Gerbers
Identify which pads use via-in-pad and whether they are signal, thermal, or current-carrying structures.
Specify the protection structure on the fabrication drawing, ideally with IPC-4761 terminology.
Confirm whether the assembler expects filled and capped, plugged, or offset thermal vias for the package family.
Review paste aperture segmentation for any exposed pad that contains vias.
Check whether the board house treats VIPPO as a standard capability or a special process with added lead time.
Run a DFM review before procurement so the fabricator and assembler agree on the same stackup and via note.
Related Reading on PCB Layout and Manufacturing
If you are working through a dense SMT layout, pair this guide with our articles on PCB trace width calculation, Gerber file preparation, and PCB assembly services. If the package is still in selection, our annular ring PCB design guide and prototype PCB service page help tighten the DFM side before layout is locked.
References
- IPC-4761, Design Guide for Protection of Printed Board Via Structures. IPC
- IPC technical resource, IPC-2221, Keeping Pace With. IPC resource
- Analog Devices, How to Design a PCB Layout for Highest Half-Bridge GaN Driver Performance. analog.com
- Infineon, Recommendations for Board Assembly of Integrated Packages without Leads. infineon.com
- Intel, Stratix 10 High Speed Signal Interface Layout Design Guideline. intel.com
- TI SMT packaging application note index for package-specific land pattern and PCB attachment guidance. ti.com
Frequently Asked Questions
Is via-in-pad the same thing as VIPPO?
Not exactly. Via-in-pad describes the via location. VIPPO usually means the via is in the pad, filled, planarized, and plated over so the surface remains solderable. That is much safer for SMT assembly than an open via in the pad.
When should I avoid via-in-pad?
Avoid it when a standard dog-bone fanout or offset thermal-via pattern meets the routing and thermal target. If the package is not space-constrained, via-in-pad often adds process cost without improving the product.
Why do open vias in pads cause bad solder joints?
During reflow, the via behaves like a capillary path. Solder can wick into the hole, leaving too little solder on the component pad. That can reduce stand-off, increase voiding, or create a weak joint.
What IPC via structure is recommended for via-in-pad?
IPC technical guidance points designers toward Type VII, the filled-and-capped structure, when specifying via-in-pad for solderable pad applications.
Do thermal pads always need VIPPO?
No. Many thermal pads work well with carefully placed via arrays plus segmented paste apertures. VIPPO becomes more attractive when planarity, dense package geometry, or solder control leave little margin.
Does via-in-pad increase cost and lead time?
Usually yes, because fill, planarization, and capping add process steps. The exact increase depends on the board house, volume, and whether the board is already using HDI features.
Need a DFM Review Before You Release a Dense PCB?
We help engineering teams review pad structures, stackups, via notes, and assembly risk before a dense BGA or power board goes to fabrication.
Request a PCB Review